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ltc2248/ltc2247/ltc2246 1 224876fa features descriptio u applicatio s u typical applicatio u sample rate: 65msps/40msps/25msps single 3v supply (2.7v to 3.4v) low power: 205mw/120mw/75mw 74.3db snr 90db sfdr no missing codes flexible input: 1v p-p to 2v p-p range 575mhz full power bandwidth s/h clock duty cycle stabilizer shutdown and nap modes pin compatible family 125msps: ltc2253 (12-bit), ltc2255 (14-bit) 105msps: ltc2252 (12-bit), ltc2254 (14-bit) 80msps: ltc2229 (12-bit), ltc2249 (14-bit) 65msps: ltc2228 (12-bit), ltc2248 (14-bit) 40msps: ltc2227 (12-bit), ltc2247 (14-bit) 25msps: ltc2226 (12-bit), ltc2246 (14-bit) 10msps: ltc2225 (12-bit), ltc2245 (14-bit) 32-pin (5mm 5mm) qfn package 14-bit, 65/40/25msps low power 3v adcs the ltc 2248/ltc2247/ltc2246 are 14-bit 65msps/ 40msps/25msps, low power 3v a/d converters designed for digitizing high frequency, wide dynamic range signals. the ltc2248/ltc2247/ltc2246 are perfect for demand- ing imaging and communications applications with ac performance that includes 74.3db snr and 90db sfdr for signals at the nyquist frequency. dc specs include 1lsb inl (typ), 0.5lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.6v logic. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. + input s/h correction logic output drivers 14-bit pipelined adc core clock/duty cycle control flexible reference d13 d0 clk refh refl analog input 2249 ta01a ov dd ognd input frequency (mhz) 0 snr (dbfs) 200 2249 tao1b 50 100 150 75 74 73 72 71 70 ltc2248: snr vs input frequency, ?db, 2v range, 65msps wireless and wired broadband communication imaging systems ultrasound spectral analysis portable instrumentation , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2248/ltc2247/ltc2246 2 224876fa absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... 0.3v to 1v analog input voltage (note 3) ..... 0.3v to (v dd + 0.3v) digital input voltage .................... 0.3v to (v dd + 0.3v) digital output voltage ................ 0.3v to (ov dd + 0.3v) power dissipation ............................................ 1500mw operating temperature range ltc2248c, ltc2247c, ltc2246c ........... 0 c to 70 c ltc2248i, ltc2247i, ltc2246i ..........40 c to 85 c storage temperature range ..................65 c to 125 c the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) ltc2248 ltc2247 ltc2246 parameter conditions min typ max min typ max min typ max units resolution 14 14 14 bits (no missing codes) integral differential analog input ? 144 144 14 lsb linearity error (note 5) differential differential analog input ? 0.5 1 1 0.5 1 1 0.5 1 lsb linearity error offset error (note 6) ?2 21212 21212 212 mv gain error external reference 2.5 0.5 2.5 2.5 0.5 2.5 2.5 0.5 2.5 %fs offset drift 10 10 10 v/ c full-scale drift internal reference 30 30 30 ppm/ c external reference 5 5 5 ppm/ c transition noise sense = 1v 1 1 1 lsb rms co verter characteristics u t jmax = 125 c, ja = 34 c/w exposed pad is gnd (pin 33) must be soldered to pcb 32 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 ain + ain refh refh refl refl v dd gnd d10 d9 d8 ov dd ognd d7 d6 d5 v dd v cm sense mode of d13 d12 d11 clk shdn oe d0 d1 d2 d3 d4 33 order part number consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. ltc2248cuh ltc2248iuh ltc2247cuh LTC2247IUH ltc2246cuh ltc2246iuh order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ qfn part marking* 2248 2248 2247 2247 2246 2246
ltc2248/ltc2247/ltc2246 3 224876fa symbol parameter conditions min typ max units v in analog input range (a in + ?a in ) 2.7v < v dd < 3.4v (note 7) 0.5v to 1v v v in,cm analog input common mode (a in + + a in )/2 differential input (note 7) 1 1.5 1.9 v single ended input (note 7) 0.5 1.5 2 v i in analog input leakage current 0v < a in + , a in < v dd ? 1 a i sense sense input leakage 0v < sense < 1v ? 3 a i mode mode pin leakage ? 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 575 mhz the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = ?dbfs. (note 4) ltc2248 ltc2247 ltc2246 symbol parameter conditions min typ max min typ max min typ max units snr signal-to-noise ratio 5mhz input 74.3 74.4 74.5 db 12.5mhz input 72.9 74.2 db 20mhz input 72.9 74.4 db 30mhz input 72.5 74.3 db 70mhz input 74.3 73.9 73.4 db 140mhz input 73.9 73.3 73 db sfdr 5mhz input 90 90 90 db 12.5mhz input 76 90 db 20mhz input 76 90 db 30mhz input 76 90 db 70mhz input 85 85 85 db 140mhz input 80 80 80 db sfdr 5mhz input 95 95 95 db 12.5mhz input 84 95 db 20mhz input 84 95 db 30mhz input 84 95 db 70mhz input 95 95 95 db 140mhz input 90 90 90 db s/(n+d) 5mhz input 74.3 74.4 74.5 db 12.5mhz input 72.2 74.2 db 20mhz input 72.2 74.3 db 30mhz input 72 74.2 db 70mhz input 74.1 73.6 73.4 db 140mhz input 71.9 71.9 71.8 db i md intermodulation f in1 = 28.2mhz 90 90 90 db distortion f in2 = 26.8mhz a alog i put u u dy a ic accuracy u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) signal-to-noise plus distortion ratio spurious free dynamic range 4th harmonic or higher spurious free dynamic range 2nd or 3rd harmonic
ltc2248/ltc2247/ltc2246 4 224876fa digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) i ter al refere ce characteristics uu u (note 4) power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 8) ltc2248 ltc2247 ltc2246 symbol parameter conditions min typ max min typ max min typ max units v dd analog supply (note 9) 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 v voltage ov dd output supply (note 9) 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 v voltage iv dd supply current 68.3 80 40 48 25 30 ma p diss power dissipation 205 240 120 144 75 90 mw p shdn shutdown power shdn = h, 2 2 2 mw oe = h, no clk p nap nap mode power shdn = h, 15 15 15 mw oe = l, no clk parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 25 ppm/ c v cm line regulation 2.7v < v dd < 3.4v 3 mv/v v cm output resistance ?ma < i out < 1ma 4 ? symbol parameter conditions min typ max units logic inputs (clk, oe, shdn) v ih high level input voltage v dd = 3v 2v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd ?0 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = ?0 a 2.995 v i o = ?00 a 2.7 2.99 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = ?00 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = ?00 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v
ltc2248/ltc2247/ltc2246 5 224876fa ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 65mhz (ltc2248), 40mhz (ltc2247), or 25mhz (ltc2246), input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from 0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 65mhz (ltc2248), 40mhz (ltc2247), or 25mhz (ltc2246), input range = 1v p-p with differential drive. note 9: recommended operating conditions. ltc2248 ltc2247 ltc2246 symbol parameter conditions min typ max min typ max min typ max units f s sampling frequency (note 9) 165140125mhz t l clk low time duty cycle stabilizer off 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns duty cycle stabilizer on 5 7.7 500 5 12.5 500 5 20 500 ns (note 7) t h clk high time duty cycle stabilizer off 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns duty cycle stabilizer on 5 7.7 500 5 12.5 500 5 20 500 ns (note 7) t ap sample-and-hold 0 0 0 ns aperture delay t d clk to data delay c l = 5pf (note 7) 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns data access time c l = 5pf (note 7) 4.3 10 4.3 10 4.3 10 ns after oe bus relinquish time (note 7) 3.3 8.5 3.3 8.5 3.3 8.5 ns pipeline 5 5 5 cycles latency ltc2248: typical dnl, 2v range, 65msps ltc2248: typical inl, 2v range, 65msps code 0 inl error (lsb) 12288 2248 g01 4096 8192 16384 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 code 0 dnl error (lsb) 12288 2248 g02 4096 8192 16384 1.00 0.75 0.50 0.25 0 0.25 0.50 0.75 1.00 typical perfor a ce characteristics uw
ltc2248/ltc2247/ltc2246 6 224876fa frequency (mhz) 0 amplitude (db) 2248 g03 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) 0 amplitude (db) 2248 g04 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) 0 amplitude (db) 2248 g05 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) 0 amplitude (db) 2248 g06 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) 0 amplitude (db) 2248 g06a 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 code 8196 8197 8198 8199 8200 8201 8202 8203 121 1596 9042 21824 20412 10224 2116 172 count 2248 g08 25000 20000 15000 10000 5000 0 input frequency (mhz) 0 snr (dbfs) 200 2248 g09 50 100 150 75 74 73 72 71 70 input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 2248 g10 50 100 200 sfdr (dbfs) typical perfor a ce characteristics uw ltc2248: 8192 point fft, f in = 5mhz, ?db, 2v range, 65msps ltc2248: 8192 point fft, f in = 30mhz, ?db, 2v range, 65msps ltc2248: 8192 point fft, f in = 70mhz, ?db, 2v range, 65msps ltc2248: 8192 point fft, f in = 140mhz, ?db, 2v range, 65msps ltc2248: grounded input histogram, 65msps ltc2248: snr vs input frequency, ?db, 2v range, 65msps ltc2248: sfdr vs input frequency, ?db, 2v range, 65msps ltc2248: 8192 point 2-tone fft, f in = 28.2mhz and 26.8mhz, ?db, 2v range, 65msps
ltc2248/ltc2247/ltc2246 7 224876fa sample rate (msps) i vdd (ma) 2248 g15 80 75 70 65 60 55 50 0 20 40 50 10 30 60 70 80 2v range 1v range clock duty cycle (%) snr and sfdr (dbfs) 2247 g12 100 95 90 85 80 75 70 30 40 50 55 35 45 60 65 70 sample rate (msps) 50 snr and sfdr (dbfs) 110 100 90 80 70 60 100 2248 g11 60 70 80 90 010 20 30 40 110 sfdr: dcs on snr: dcs on snr: dcs off sfdr: dcs off input level (dbfs) ?0 50 snr (dbc and dbfs) ?0 20 ?0 ?0 0 2248 g13 input level (dbfs) 60 50 40 20 ?0 ?0 0 2248 g14 80 70 60 50 40 30 20 10 0 sfdr (dbc and dbfs) 120 110 100 90 80 70 60 50 40 30 20 dbfs dbfs dbc dbc 90dbc sfdr reference line sample rate (msps) i ovdd (ma) 2248 g16 6 5 4 3 2 1 0 0 20 40 50 10 30 60 70 80 code 0 inl error (lsb) 12288 2247 g01 4096 8192 16384 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 code 0 dnl error (lsb) 12288 2247 g02 4096 8192 16384 1.00 0.75 0.50 0.25 0 0.25 ?.50 ?.75 ?.00 frequency (mhz) amplitude (db) 2247 g03 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 0 5101520 snr sfdr typical perfor a ce characteristics uw ltc2248: snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db ltc2248: snr and sfdr vs clock duty cycle, 65msps ltc2248: snr vs input level, f in = 30mhz, 2v range, 65msps ltc2248: i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v ltc2248: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2247: typical inl, 2v range, 40msps ltc2247: typical dnl, 2v range, 40msps ltc2247: 8192 point fft, f in = 5mhz, ?db, 2v range, 40msps ltc2248: sfdr vs input level, f in = 30mhz, 2v range, 65msps
ltc2248/ltc2247/ltc2246 8 224876fa typical perfor a ce characteristics uw frequency (mhz) 0 amplitude (db) 2247 g04 5101520 0 5101520 0 5101520 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) amplitude (db) 2247 g05 frequency (mhz) amplitude (db) 2247 g06 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 code 8184 8185 8186 818781888189 8190 81918192 546 36 15714 24558 14833 640 4641 30 count 2247 g08 30000 25000 20000 15000 10000 5000 0 input frequency (mhz) 0 snr (dbfs) 200 2247 g09 50 100 150 75 74 73 72 71 70 4520 frequency (mhz) 0 amplitude (db) 2247 g07 5 101520 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 sample rate (msps) 0 snr and sfdr (dbfs) 110 100 90 80 70 60 80 2247 g11 40 20 60 snr sfdr input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 2247 g10 50 100 200 sfdr (dbfs) input level (dbfs) ?0 50 snr (dbc and dbfs) ?0 20 ?0 ?0 0 2247 g12 80 70 60 50 40 30 20 10 0 dbfs dbc ltc2247: 8192 point fft, f in = 30mhz, ?db, 2v range, 40msps ltc2247: 8192 point fft, f in = 70mhz, ?db, 2v range, 40msps ltc2247: 8192 point fft, f in = 140mhz, ?db, 2v range, 40msps ltc2247: 8192 point 2-tone fft, f in = 21.6mhz and 23.6mhz, ?db, 2v range, 40msps ltc2247: grounded input histogram, 40msps ltc2247: snr vs input frequency, ?db, 2v range, 40msps ltc2247: sfdr vs input frequency, ?db, 2v range, 40msps ltc2247: snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db ltc2247: snr vs input level, f in = 5mhz, 2v range, 40msps
ltc2248/ltc2247/ltc2246 9 224876fa code 0 inl error (lsb) 12288 2246 g01 4096 8192 16384 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 code 0 dnl error (lsb) 12288 2246 g02 4096 8192 16384 frequency (mhz) 0 amplitude (db) 2246 g03 246810 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) 0 amplitude (db) 2246 g04 246810 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) 0 amplitude (db) 2246 g05 246810 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 frequency (mhz) 0 amplitude (db) 2246 g06 246810 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 1.00 0.75 0.50 0.25 0 0.25 ?.50 ?.75 ?.00 input level (dbfs) 60 50 40 20 ?0 ?0 0 2247 g13 snr (dbc and dbfs) 120 110 100 90 80 70 60 50 40 30 20 dbfs dbc 90dbc sfdr reference line sample rate (msps) 0 i vdd (ma) 40 2247 g14 10 20 30 50 50 45 40 35 30 2v range 1v range sample rate (msps) 0 i ovdd (ma) 2 3 40 2247 g15 1 0 10 20 30 50 4 ltc2247: i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v ltc2247: i vdd vs sample rate, 5mhz sine wave input, ?db typical perfor a ce characteristics uw ltc2247: sfdr vs input level, f in = 5mhz, 2v range, 40msps ltc2246: typical inl, 2v range, 25msps ltc2246: typical dnl, 2v range, 25msps ltc2246: 8192 point fft, f in = 5mhz, ?db, 2v range, 25msps ltc2246: 8192 point fft, f in = 30mhz, ?db, 2v range, 25msps ltc2246: 8192 point fft, f in = 70mhz, ?db, 2v range, 25msps ltc2246: 8192 point fft, f in = 140mhz, ?db, 2v range, 25msps
ltc2248/ltc2247/ltc2246 10 224876fa code 8179 8180 8181 8182 8183 8184 8185 8186 3227 278 18803 22016 853 6919 43 count 2246 g08 25000 20000 15000 10000 5000 0 input frequency (mhz) 0 snr (dbfs) 200 2246 g09 50 100 150 75 74 73 72 71 70 13373 frequency (mhz) 0 amplitude (db) 2246 g07 246810 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 sample rate (msps) i vdd (ma) 2246 g14 35 30 25 20 15 0 10 20 515 25 30 35 0 10 20 515 25 30 35 2v range 1v range input level (dbfs) snr (dbc and dbfs) 2246 g12 80 70 60 50 40 30 20 10 0 ?0 ?0 ?0 ?0 ?0 ?0 0 sample rate (msps) 0 snr and sfdr (dbfs) 110 100 90 80 70 60 2246 g11 10 20 30 40 50 snr input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 2246 g10 50 100 200 sfdr (dbfs) input level (dbfs) 60 50 40 20 ?0 ?0 0 2246 g13 sfdr (dbc and dbfs) 120 110 100 90 80 70 60 50 40 30 20 dbfs dbc 90dbc sfdr reference line sample rate (msps) i ovdd (ma) 2246 g15 3 2 1 0 dbfs dbc sfdr typical perfor a ce characteristics uw ltc2246: 8192 point 2-tone fft, f in = 10.9mhz and 13.8mhz, ?db, 2v range, 25msps ltc2246: grounded input histogram, 25msps ltc2246: snr vs input frequency, ?db, 2v range, 25msps ltc2246: sfdr vs input frequency, ?db, 2v range, 25msps ltc2246: snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db ltc2246: snr vs input level, f in = 5mhz, 2v range, 25msps ltc2246: i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v ltc2246: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2246: sfdr vs input level, f in = 5mhz, 2v range, 25msps
ltc2248/ltc2247/ltc2246 11 224876fa uu u pi fu ctio s a in + (pin 1): positive differential analog input. a in - (pin 2): negative differential analog input. refh (pins 3, 4): adc high reference. short together and bypass to pins 5, 6 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. refl (pins 5, 6): adc low reference. short together and bypass to pins 3, 4 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 3, 4 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. v dd (pins 7, 32): 3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. gnd (pin 8): adc power ground. clk (pin 9): clock input. the input sample starts on the positive edge. shdn (pin 10): shutdown mode selection pin. connect- ing shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin 11): output enable pin. refer to shdn pin function. d0 ?d13 (pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): digital outputs. d13 is the msb. ognd (pin 20): output driver ground. ov dd (pin 21): positive supply for the output drivers. bypass to ground with 0.1 f ceramic chip capacitor. of (pin 28): over/under flow output. high when an over or under flow has occurred. mode (pin 29): output format and clock duty cycle stabilizer selection pin. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2? complement output format and turns the clock duty cycle stabilizer on. v dd selects 2? complement output format and turns the clock duty cycle stabilizer off. sense (pin 30): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 31): 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. gnd (exposed pad) (pin 33): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground.
ltc2248/ltc2247/ltc2246 12 224876fa fu n ctio n al block diagra uu w shift register and correction diff ref amp ref buf 2.2 f 1 f1 f 0.1 f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe m0de ognd ov dd 224876 f01 input s/h sense v cm a in a in + 2.2 f third pipelined adc stage output drivers control logic shdn of d13 d0 figure 1. functional block diagram t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n ?4 n ?3 n ?2 n ?1 clk d0-d13, of 224876 td01 n ?5 n timing diagram ti i g diagra u ww
ltc2248/ltc2247/ltc2246 13 224876fa dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ( (v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1) where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa ?fb and 2fb ?fa. the intermodulation distortion is defined as the ratio of the rms value of either applicatio s i for atio wu uu input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = ?0log (2 ?f in ?t jitter ) converter operation as shown in figure 1, the ltc2248/ltc2247/ltc2246 is a cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value five cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2248/ltc2247/ltc2246 has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the
ltc2248/ltc2247/ltc2246 14 224876fa dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the ?nput s/h?shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2248/ ltc2247/ltc2246 cmos differential sample-and-hold. the analog inputs are connected to the sampling capaci- tors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summa- tion of all other capacitance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are applicatio s i for atio wu u u disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in should be connected to 1.5v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin (pin 31) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. figure 2. equivalent input circuit v dd v dd v dd 15 ? 15 ? c parasitic 1pf c parasitic 1pf c sample 4pf c sample 4pf ltc2248/47/46 a in + a in clk 224876 f02
ltc2248/ltc2247/ltc2246 15 224876fa input drive impedance as with all high performance, high speed adcs, the dynamic performance of the ltc2248/ltc2247/ltc2246 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can influence sfdr. at the falling edge of clk, the sample-and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2248/ltc2247/ltc2246 being driven by an rf transformer with a center tapped second- ary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 ? for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies be- low 1mhz. figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies. applicatio s i for atio wu uu figure 5. single-ended drive figure 3. single-ended to differential conversion using a transformer 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in 12pf 2.2 f v cm ltc2248/47/46 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 224876 f03 figure 4. differential drive with an amplifier 25 ? 25 ? 12pf 2.2 f v cm ltc2248/47/46 224876 f04 + + cm analog input high speed differential amplifier a in + a in 25 ? 0.1 f analog input v cm a in + a in 1k 12pf 224876 f05 2.2 f 1k 25 ? 0.1 f ltc2248/47/46 figure 5 shows a single-ended input circuit. the imped- ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. the 25 ? resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input.
ltc2248/ltc2247/ltc2246 16 224876fa for input frequencies above 70mhz, the input circuits of figure 6, 7 and 8 are recommended. the balun trans- former gives better high frequency response than a flux coupled center tapped transformer. the coupling capaci- tors allow the analog inputs to be dc biased at 1.5v. in figure 8, the series inductors are impedance matching elements that maximize the adc bandwidth. applicatio s i for atio wu uu figure 6. recommended front end circuit for input frequencies between 70mhz and 170mhz 25 ? 25 ? 12 ? 12 ? 0.1 f a in + a in 8pf 2.2 f v cm ltc2248/47/46 analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 224876 f06 figure 8. recommended front end circuit for input frequencies above 300mhz 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm ltc2248/47/46 analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 224876 f07 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm ltc2248/47/46 analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors, inductors are 0402 package size 224876 f08 6.8nh 6.8nh figure 7. recommended front end circuit for input frequencies between 170mhz and 300mhz v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ?v sense for 0.5v < v sense < v cm ? 1.5v refl 2.2 f 2.2 f internal adc high reference buffer 0.1 f 224876 f09 ltc2248/47/46 4 ? diff amp 1 f 1 f internal adc low reference 1.5v bandgap reference 1v 0.5v range detect and control 1.1 1.5 figure 9. equivalent reference circuit reference operation figure 9 shows the ltc2248/ltc2247/ltc2246 refer- ence circuitry consisting of a 1.5v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage reference can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output
ltc2248/ltc2247/ltc2246 17 224876fa applicatio s i for atio wu uu pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise perfor- mance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5.8db. see the typical performance charac- teristics section. driving the clock input the clk input can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with figure 10. 1.5v range adc clk 50 ? 0.1 f 0.1 f 4.7 f 1k 1k ferrite bead clean supply sinusoidal clock input 224876 f11 nc7svu04 ltc2248/47/46 figure 11. sinusoidal single-ended clk drive a low-jitter squaring circuit before the clk pin (see figure 11). the noise performance of the ltc2248/ltc2247/ltc2246 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digitiz- ing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, filter the clk signal to reduce wideband noise and distortion products generated by the source. figures 12 and 13 show alternatives for converting a differential clock to the single-ended clk input. the use of a transformer provides no incremental contribution to phase noise. the lvds or pecl to cmos translators provide little degradation below 70mhz, but at 140mhz will degrade the snr compared to the transformer solu- tion. the nature of the received signals also has a large v cm sense 1.5v 0.75v 2.2 f 12k 1 f 12k 224876 f10 ltc2248/47/46 figure 12. clk drive using an lvds or pecl to cmos converter clk 100 ? 0.1 f 4.7 f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 224876 f12 ltc2248/ ltc2247/ ltc2246 clk 5pf-30pf etc1-1t 0.1 f v cm ferrite bead differential clock input 224876 f13 ltc2248/ ltc2247/ ltc2246 figure 13. lvds or pecl clk drive using a transformer
ltc2248/ltc2247/ltc2246 18 224876fa applicatio s i for atio wu uu bearing on how much snr degradation will be experi- enced. for high crest factor signals such as wcdma or ofdm, where the nominal power level must be at least 6db to 8db below full scale, the use of these translators will have a lesser impact. the transformer in the example may be terminated with the appropriate termination for the signaling in use. the use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. the center tap may be bypassed to ground through a capacitor close to the adc if the differential signals originate on a different plane. the use of a capaci- tor at the input may result in peaking, and depending on transmission line length may require a 10 ? to 20 ? ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mecha- nism for reflections. maximum and minimum conversion rates the maximum conversion rate for the ltc2248/ltc2247/ ltc2246 is 65msps (ltc2248), 40msps (ltc2247), and 25msps (ltc2246). for the adc to operate properly, the clk signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 7.3ns (ltc2248), 11.8ns (ltc2247), and 18.9ns (ltc2246) for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the ltc2248/ltc2247/ltc2246 sample rate is determined by droop of the sample-and-hold cir- cuits. the pipelined architecture of this adc relies on figure 14. digital output buffer ltc2248/47/46 224876 f12 ov dd v dd v dd 0.1 f 43 ? typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch oe table 1. output codes vs input voltage a in + ?a in d13 ?d0 d13 ?d0 (2v range) of (offset binary) (2? complement) >+1.000000v 1 11 1111 1111 1111 01 1111 1111 1111 +0.999878v 0 11 1111 1111 1111 01 1111 1111 1111 +0.999756v 0 11 1111 1111 1110 01 1111 1111 1110 +0.000122v 0 10 0000 0000 0001 00 0000 0000 0001 0.000000v 0 10 0000 0000 0000 00 0000 0000 0000 ?.000122v 0 01 1111 1111 1111 11 1111 1111 1111 ?.000244v 0 01 1111 1111 1110 11 1111 1111 1110 ?.999878v 0 00 0000 0000 0001 10 0000 0000 0001 ?.000000v 0 00 0000 0000 0000 10 0000 0000 0000 ltc2248/ltc2247/ltc2246 19 224876fa applicatio s i for atio wu uu as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2248/ltc2247/ltc2246 should drive a minimal capacitive load to avoid possible interac- tion between the digital outputs and sensitive input cir- cuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. data format using the mode pin, the ltc2248/ltc2247/ltc2246 parallel digital output can be selected for offset binary or 2? complement format. connecting mode to gnd or 1/3v dd selects offset binary output format. connecting mode to 2/3v dd or v dd selects 2? complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 2 shows the logic states for the mode pin. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of. the data ac- cess and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed op- eration. the output hi-z state is intended for use during long periods of inactivity. sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 15mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. table 2. mode pin function clock duty mode pin output format cycle stablizer 0 offset binary off 1/3v dd offset binary on 2/3v dd 2? complement on v dd 2? complement off overflow bit when of outputs a logic high the converter is either overranged or underranged.
ltc2248/ltc2247/ltc2246 20 224876fa grounding and bypassing the ltc2248/ltc2247/ltc2246 requires a printed cir- cuit board with a clean, unbroken ground plane. a multi- layer board with an internal ground plane is recom- mended. layout for the printed circuit board should en- sure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. of particular importance is the 0.1 f capacitor between refh and refl. this capacitor should be placed as close to the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2 f ca- pacitor between refh and refl can be somewhat further away. the traces connecting the pins and bypass capaci- tors must be kept short and should be made as wide as possible. the ltc2248/ltc2247/ltc2246 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2248/ltc2247/ ltc2246 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. for good electrical and thermal perfor- mance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area. clock sources for undersampling undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a 3v canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the adc may be beneficial. this filter should be close to the adc to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the adc. if you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the driver to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re- timing flip-flop as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multi- layer pcbs. the differential pairs must be close together and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. applicatio s i for atio wu uu
ltc2248/ltc2247/ltc2246 21 224876fa applicatio s i for atio wu uu 1 2 c8 0.1 f c11 0.1 f 3 4 5 v dd 7 v dd v dd gnd 9 32 v cm 31 30 29 33 jp2 oe 10 11 8 c7 2.2 f c6 1 f c9 1 f c4 0.1 f c2 8.2pf v dd v dd v dd gnd jp1 shdn c15 2.2 f c16 0.1 f c18 0.1 f c25 4.7 f e2 v dd 3v e4 pwr gnd v dd v cc 22554 ta02 c17 0.1 f c20 0.1 f c19 0.1 f c14 0.1 f r10 33 ? e1 ext ref r14 1k r15 1k r16 1k r7 1k r8 49.9 ? r3 24.9 ? r2 12.4 ? r6 12.4 ? r1 opt r4 24.9 ? r5 50 ? t1 etc1-1t c1 0.1 f c3 0.1 f j3 clock input nc7svu04 nc7svu04 c13 0.1 f c10 0.1 f c5 4.7 f 6.3v l1 bead v dd c12 0.1 f r9 1k j1 analog input a in + a in refh refh 6 refl refl v dd clk shdn v dd v cm sense mode gnd ltc2248/ltc2247/ ltc2246 oe d12 d11 gnd d0 d1 d2 d3 d5 d4 d6 d8 d9 d13 of ov dd v cc ognd d10 d7 26 25 12 13 14 15 17 16 18 22 23 27 28 21 20 24 19 oe1 i 0 oe2 le1 le2 v cc v cc v cc gnd gnd gnd i 1 i 2 i 4 i 3 i 5 i 7 i 8 i 12 i 11 i 10 i 13 i 14 i 15 i 9 o11 o10 i 6 v cc o0 gnd gnd gnd v cc v cc gnd 34 45 39 42 25 48 24 1 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 v cc 28 74vcx16373mtd 31 21 15 18 10 4 7 r n1c 33 ? 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 gnd o1 o2 o4 o3 o5 o7 o8 o12 o13 o14 o15 o9 o6 25 23 27 29 31 33 35 37 39 21 19 15 17 13 9 7 1 3 5 2 4 11 26 24 30 28 34 32 38 40 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 3201s-40g1 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 36 a3 a2 a1 a0 sda wp v cc 1 2 3 4 8 24lc025 7 6 5 scl 22 20 16 18 14 10 8 6 12 1 2 3 5 4 v cm 12 v dd v dd 34 2/3v dd 56 1/3v dd 78 gnd jp4 mode 12 v dd 34 v cm v dd v cm 56 ext ref jp3 sense r n1b 33 ? r n1a 33 ? r n2d 33 ? r n2c 33 ? r n2b 33 ? r n2a 33 ? r n3d 33 ? r n3c 33 ? r n3b 33 ? r n3a 33 ? r n4d 33 ? r n4b 33 ? r n4a 33 ? r13 10k r11 10k r12 10k r n4c 33 ? r n1d 33 ? c28 1 f c27 0.01 f v cc v dd nc7sv86p5x byp gnd adj out shdn gnd in 1 2 3 4 8 lt1763 7 6 5 gnd r18 100k r17 105k c26 10 f 6.3v e3 gnd c21 0.1 f c22 0.1 f c23 0.1 f c24 0.1 f evaluation circuit schematic of the ltc2248/ltc2247/ltc2246
ltc2248/ltc2247/ltc2246 22 224876fa applicatio s i for atio wu u u silkscreen top topside inner layer 2 gnd inner layer 3 power
ltc2248/ltc2247/ltc2246 23 224876fa applicatio s i for atio wu u u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 0.23 typ (4 sides) 31 1 2 32 bottom view?xposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0603 0.50 bsc 0.200 ref 0.00 ?0.05 0.70 0.05 3.45 0.05 (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) package descriptio u bottomside silkscreen bottom
ltc2248/ltc2247/ltc2246 24 224876fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0106 rev a ? printed in usa related parts part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential low distortion: ?4dbc at 1mhz input/output amplifier/driver ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2225 12-bit, 10msps, 3v adc, lowest power 60mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2226 12-bit, 25msps, 3v adc, lowest power 75mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2227 12-bit, 40msps, 3v adc, lowest power 120mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2228 12-bit, 65msps, 3v adc, lowest power 205mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2229 12-bit, 80msps, 3v adc, lowest power 211mw, 70.6db snr, 90db sfdr, 32-pin qfn ltc2236 10-bit, 25msps, 3v adc, lowest power 75mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2237 10-bit, 40msps, 3v adc, lowest power 120mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2238 10-bit, 65msps, 3v adc, lowest power 205mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2239 10-bit, 80msps, 3v adc, lowest power 211mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2245 14-bit, 10msps, 3v adc, lowest power 60mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2246 14-bit, 25msps, 3v adc, lowest power 75mw, 74.5db snr, 90db sfdr, 32-pin qfn ltc2247 14-bit, 40msps, 3v adc, lowest power 120mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2248 14-bit, 65msps, 3v adc, lowest power 205mw, 74.3db snr, 90db sfdr, 32-pin qfn ltc2249 14-bit, 80msps, 3v adc, lowest power 222mw, 73db snr, 90db sfdr, 32-pin qfn ltc2250 10-bit, 105msps, 3v adc, lowest power 320mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2251 10-bit, 125msps, 3v adc, lowest power 395mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2252 12-bit, 105msps, 3v adc, lowest power 320mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2253 12-bit, 125msps, 3v adc, lowest power 395mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2254 14-bit, 105msps, 3v adc, lowest power 320mw, 72.4db snr, 88db sfdr, 32-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifier/adc driver 450mhz to 1db bw, 47db oip3, with digitally controlled gain digital gain control 10.5db to 33ddb in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 ? single-ended rf and lo ports

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